Title | : | The best way to start learning Verilog |
Lasting | : | 14.50 |
Date of publication | : | |
Views | : | 159 rb |
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amazing thank you so much Comment from : @LukeAlbert-v9f |
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Thank you very much! Comment from : @EmanuelRaziel |
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I will have to watch again Alas, without a trainer kit to piddle with this, it's all either-gas Comment from : @alanmolox2095 |
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This was a very interesting and great video Thank you very muchbrBut i have one questions Your 3 code examples for Gate, Dataflow and Behavioral Level do produce the same end result, but does it also generate the same hardware inside the FPGA? brI'm asking because I would like to know if the design was much more complex, eg a CPU implemented in an FPGA, would the CPUs of the 3 codying style variants be the same with the same performance?brOr would it be possible, for example, that the dataflow level variant generates a faster CPU on the FGPA than a CPU based on the behavior level variant and vice versa? Comment from : @OpenGL4ever |
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Thank you Comment from : @iainwilliamwiseman4602 |
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Thank you Comment from : @sangtruong8833 |
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Excellent video Is there by chance a continuation from this video to teach more about Verilog? That would be much appreciated! Comment from : @spearius9059 |
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You explain everything so well! Even the most complex things Comment from : @sam-kx3ty |
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superb vedio Comment from : @redtoxicextazy |
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Miller Helen Clark Carol Lewis Scott Comment from : @VincentAnnabelle-l4l |
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Maximilian Locks Comment from : @JohnGarcia-j5r |
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Schumm Neck Comment from : @JerryKirk-y9k |
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Excellent 🫡 Comment from : @esijal |
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Is Gate level design same a Structural design in Verilog ? Comment from : @temporary9508 |
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Wow wow wow! , I am a total beginner to verilog and this video helped so much for my lab exam due in a few days Thank you! Comment from : @GayathriG-j7h |
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Thank you so much and kudos to you for making this marvelous video! Comment from : @Kaamanita |
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I don't have any background in this subject, but I want to know why, at the data flow level, he used `((X & A) & A) | (X & B)` and not `(X & A) | (X & B)` Comment from : @emanon2315 |
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What software are you using? Comment from : @ayanacharya9747 |
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great Comment from : @eggxecution |
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You dropped the science down so smooth on this video manbrMuch respect 🫡 Comment from : @dustincdouglas2290 |
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Cried in class because I couldn't understand this topic Thank you for the simple explanation Comment from : @lujeanguieb7271 |
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@3:54 Why do you &A twice ? shouldn't it just be (X&A)|(X&B) ? Comment from : @sajanjeka677 |
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Why the firs example is not (X & A) | (B & X) instead of ((X & A) & A) | (B & X)? Why do we need the extra "& A"? Comment from : @cchsiang2002 |
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@3:56 Why (X&A)&A) instead of X&A ? Comment from : @AK-vx4dy |
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Which tool you using ? Comment from : @ladolahiral5007 |
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Blocking or non-blocking assignments can give you either combinational or sequential logic depending on the sensitivity list of the always block these assignments are included in Comment from : @e630fnr |
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Thank u Comment from : @Oppppppppppppppppp |
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the behavioural level is a bit like reactive programming which is something I'm familiar with as a web developer Comment from : @SamualN |
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00:01 Verilog coding involves three different layers of abstraction and understanding the difference between combinational and sequential logic is importantbr01:59 Modeling in Verilog at the gate level involves instantiating each logic gate independently and connecting them together using wiresbr03:46 Behavioral level Verilog code describes circuit behavior at a high abstraction levelbr05:40 Multiplexer can be implemented in different ways: gate level, data flow level, and behavioral levelbr07:31 Utilize D-type flip-flops for sequential logicbr09:14 Blocking and non-blocking assignments have different evaluation and assignment processesbr11:03 Understanding the difference between blocking and non-blocking assignments in Verilogbr12:54 Use blocking assignments for combinational logic and non-blocking assignments for sequential logic Comment from : @OmarWaelAhmed |
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bVisual Electric/b 3:20 Why are there 2 ampersands: ((X&A)&A)? Comment from : @ayeflippum |
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Excellent explanation Comment from : @neilclay5835 |
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Prominent instruction Thank you ! Comment from : @huynhbaoduy6057 |
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What FPGA kit do you use ? Comment from : @nantes9807 |
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My first FPGA kit will be here in a few days can't wait to get stuck in! Comment from : @233kosta |
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Great video overall, other than the multiplexor code at 4:02 which could be simplified Good explanation of non-blocking vs blocking assignments Comment from : @sulphuric99 |
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08:13 starting an important explanation of non-blocking vs blocking assignments Comment from : @Hexor1211 |
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Checkout Verilog code examples here : vlsicodingblogspotcom/search/label/Verilog Comment from : @chiragpandya5040 |
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Is it term of bolean algebra?why the symbol different Comment from : @zulyadein4837 |
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Thks &;brI'm new to FPGAs & will try to watch your whole playlist brOh a question, I would like to program FPGAs via smartphone & I hope to use the smartphone as the human interface to the FPGA ??Can you point me in the right direction to get started?? Comment from : @tombouie |
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I took digital Circuits 1 and barely survives, this tutorial helped me understand what I didn't in my class Thank you! Comment from : @julio4094 |
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Awesome tutorial! I was able to follow with ease as a complete Verilog newbie Thanks! 👍 Comment from : @kandredfpv |
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I think you made a mistake here at 9:36br"Blocking" means, that the assignments are blocking, ie they run sequentially (one waits for the prior to finish) "Non-blocking" means, that the assignments do NOT block, ie they run in parallel and are evalutaed immediately Comment from : @Reanplayzz |
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👍👍👍, Comment from : @lazynet1246 |
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just outstanding Comment from : @arifnishan5646 |
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Very goog Short sweet and to the point! Your explanation of blocking and non-blocking was especially good Coming from a programming background I get wrapped around that axel constantly Comment from : @ctbram0627 |
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thank you for this video Comment from : @Vishalkumar-ez5xy |
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Outstanding! I am a Verilog newbie and was bewildered by the different Verilog programming paradigms until I watched this Thank you Comment from : @audiodiwhy2195 |
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Really good informational video Comment from : @shantanufatale7968 |
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3:30 ain't an error in that assign? Comment from : @riperboyxl3216 |
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Great video, awesome teaching style Thanks a bunch! What resources are you recommending as follows-ups? Comment from : @alfcnz |
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Very well done Thanks Comment from : @ksbs2829 |
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Would you please make a series of videos teaching DSP using this setup? Comment from : @geevnahal7926 |
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good job Comment from : @AkbarRajaei |
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good job Comment from : @AkbarRajaei |
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Wow what a great video! Thanks for taking the time to put this together! Comment from : @andrewphillip8432 |
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Can you please help us to have the Verilog code for the ifft and fft to implement in FPGA Comment from : @asherpaul4450 |
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