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The best way to start learning Verilog




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Title :  The best way to start learning Verilog
Lasting :   14.50
Date of publication :  
Views :   159 rb


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Comments The best way to start learning Verilog



@LukeAlbert-v9f
amazing thank you so much
Comment from : @LukeAlbert-v9f


@EmanuelRaziel
Thank you very much!
Comment from : @EmanuelRaziel


@alanmolox2095
I will have to watch again Alas, without a trainer kit to piddle with this, it's all either-gas
Comment from : @alanmolox2095


@OpenGL4ever
This was a very interesting and great video Thank you very muchbrBut i have one questions Your 3 code examples for Gate, Dataflow and Behavioral Level do produce the same end result, but does it also generate the same hardware inside the FPGA? brI'm asking because I would like to know if the design was much more complex, eg a CPU implemented in an FPGA, would the CPUs of the 3 codying style variants be the same with the same performance?brOr would it be possible, for example, that the dataflow level variant generates a faster CPU on the FGPA than a CPU based on the behavior level variant and vice versa?
Comment from : @OpenGL4ever


@iainwilliamwiseman4602
Thank you
Comment from : @iainwilliamwiseman4602


@sangtruong8833
Thank you
Comment from : @sangtruong8833


@spearius9059
Excellent video Is there by chance a continuation from this video to teach more about Verilog? That would be much appreciated!
Comment from : @spearius9059


@sam-kx3ty
You explain everything so well! Even the most complex things
Comment from : @sam-kx3ty


@redtoxicextazy
superb vedio
Comment from : @redtoxicextazy


@VincentAnnabelle-l4l
Miller Helen Clark Carol Lewis Scott
Comment from : @VincentAnnabelle-l4l


@JohnGarcia-j5r
Maximilian Locks
Comment from : @JohnGarcia-j5r


@JerryKirk-y9k
Schumm Neck
Comment from : @JerryKirk-y9k


@esijal
Excellent 🫡
Comment from : @esijal


@temporary9508
Is Gate level design same a Structural design in Verilog ?
Comment from : @temporary9508


@GayathriG-j7h
Wow wow wow! , I am a total beginner to verilog and this video helped so much for my lab exam due in a few days Thank you!
Comment from : @GayathriG-j7h


@Kaamanita
Thank you so much and kudos to you for making this marvelous video!
Comment from : @Kaamanita


@emanon2315
I don't have any background in this subject, but I want to know why, at the data flow level, he used `((X & A) & A) | (X & B)` and not `(X & A) | (X & B)`
Comment from : @emanon2315


@ayanacharya9747
What software are you using?
Comment from : @ayanacharya9747


@eggxecution
great
Comment from : @eggxecution


@dustincdouglas2290
You dropped the science down so smooth on this video manbrMuch respect 🫡
Comment from : @dustincdouglas2290


@lujeanguieb7271
Cried in class because I couldn't understand this topic Thank you for the simple explanation
Comment from : @lujeanguieb7271


@sajanjeka677
@3:54 Why do you &A twice ? shouldn't it just be (X&A)|(X&B) ?
Comment from : @sajanjeka677


@cchsiang2002
Why the firs example is not (X & A) | (B & X) instead of ((X & A) & A) | (B & X)? Why do we need the extra "& A"?
Comment from : @cchsiang2002


@AK-vx4dy
@3:56 Why (X&A)&A) instead of X&A ?
Comment from : @AK-vx4dy


@ladolahiral5007
Which tool you using ?
Comment from : @ladolahiral5007


@e630fnr
Blocking or non-blocking assignments can give you either combinational or sequential logic depending on the sensitivity list of the always block these assignments are included in
Comment from : @e630fnr


@Oppppppppppppppppp
Thank u
Comment from : @Oppppppppppppppppp


@SamualN
the behavioural level is a bit like reactive programming which is something I'm familiar with as a web developer
Comment from : @SamualN


@OmarWaelAhmed
00:01 Verilog coding involves three different layers of abstraction and understanding the difference between combinational and sequential logic is importantbr01:59 Modeling in Verilog at the gate level involves instantiating each logic gate independently and connecting them together using wiresbr03:46 Behavioral level Verilog code describes circuit behavior at a high abstraction levelbr05:40 Multiplexer can be implemented in different ways: gate level, data flow level, and behavioral levelbr07:31 Utilize D-type flip-flops for sequential logicbr09:14 Blocking and non-blocking assignments have different evaluation and assignment processesbr11:03 Understanding the difference between blocking and non-blocking assignments in Verilogbr12:54 Use blocking assignments for combinational logic and non-blocking assignments for sequential logic
Comment from : @OmarWaelAhmed


@ayeflippum
bVisual Electric/b 3:20 Why are there 2 ampersands: ((X&A)&A)?
Comment from : @ayeflippum


@neilclay5835
Excellent explanation
Comment from : @neilclay5835


@huynhbaoduy6057
Prominent instruction Thank you !
Comment from : @huynhbaoduy6057


@nantes9807
What FPGA kit do you use ?
Comment from : @nantes9807


@233kosta
My first FPGA kit will be here in a few days can't wait to get stuck in!
Comment from : @233kosta


@sulphuric99
Great video overall, other than the multiplexor code at 4:02 which could be simplified Good explanation of non-blocking vs blocking assignments
Comment from : @sulphuric99


@Hexor1211
08:13 starting an important explanation of non-blocking vs blocking assignments
Comment from : @Hexor1211


@chiragpandya5040
Checkout Verilog code examples here : vlsicodingblogspotcom/search/label/Verilog
Comment from : @chiragpandya5040


@zulyadein4837
Is it term of bolean algebra?why the symbol different
Comment from : @zulyadein4837


@tombouie
Thks &;brI'm new to FPGAs & will try to watch your whole playlist brOh a question, I would like to program FPGAs via smartphone & I hope to use the smartphone as the human interface to the FPGA ??Can you point me in the right direction to get started??
Comment from : @tombouie


@julio4094
I took digital Circuits 1 and barely survives, this tutorial helped me understand what I didn't in my class Thank you!
Comment from : @julio4094


@kandredfpv
Awesome tutorial! I was able to follow with ease as a complete Verilog newbie Thanks! 👍
Comment from : @kandredfpv


@Reanplayzz
I think you made a mistake here at 9:36br"Blocking" means, that the assignments are blocking, ie they run sequentially (one waits for the prior to finish) "Non-blocking" means, that the assignments do NOT block, ie they run in parallel and are evalutaed immediately
Comment from : @Reanplayzz


@lazynet1246
👍👍👍,
Comment from : @lazynet1246


@arifnishan5646
just outstanding
Comment from : @arifnishan5646


@ctbram0627
Very goog Short sweet and to the point! Your explanation of blocking and non-blocking was especially good Coming from a programming background I get wrapped around that axel constantly
Comment from : @ctbram0627


@Vishalkumar-ez5xy
thank you for this video
Comment from : @Vishalkumar-ez5xy


@audiodiwhy2195
Outstanding! I am a Verilog newbie and was bewildered by the different Verilog programming paradigms until I watched this Thank you
Comment from : @audiodiwhy2195


@shantanufatale7968
Really good informational video
Comment from : @shantanufatale7968


@riperboyxl3216
3:30 ain't an error in that assign?
Comment from : @riperboyxl3216


@alfcnz
Great video, awesome teaching style Thanks a bunch! What resources are you recommending as follows-ups?
Comment from : @alfcnz


@ksbs2829
Very well done Thanks
Comment from : @ksbs2829


@geevnahal7926
Would you please make a series of videos teaching DSP using this setup?
Comment from : @geevnahal7926


@AkbarRajaei
good job
Comment from : @AkbarRajaei


@AkbarRajaei
good job
Comment from : @AkbarRajaei


@andrewphillip8432
Wow what a great video! Thanks for taking the time to put this together!
Comment from : @andrewphillip8432


@asherpaul4450
Can you please help us to have the Verilog code for the ifft and fft to implement in FPGA
Comment from : @asherpaul4450



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